----------------------------------------------------------------------------------
-- Company: BASH Robotics
-- Engineer: Will Rozzo
-- 
-- Create Date:    13:10:29 07/18/2009 
-- Design Name: 
-- Module Name:    Central_StateMachine - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Central_StateMachine is

Port ( 	inPQPkt   : in std_logic_vector(31 downto 0);	-- 32 bit data packet, comes in from the Priority Queue
		 	inDMemPkt : in std_logic_vector(31 downto 0);   -- Packet from the data memory
		  	clk		 : in std_logic;				            -- Clock
			outRSPkt	 : out std_logic_vector(31 downto 0);  -- The packet we are sending through the RS232 to the Robot																
		  	rst		 : in std_logic;        				   -- standard mapping to the reset Reset
			CentralState : out std_logic_vector(1 downto 0) -- This is the state that is controlled here and passed to all components	
			);	            

end Central_StateMachine;

architecture RTL of Central_StateMachine is
type StateType is (IDLE, RD, WR, ST3);
signal CurrentState, NextState: StateType;
begin

--STATES
-- 00: IDLE
-- 01: READ
-- 10: WRITE
-- 11: ?? NOT USED, saved for later need if necessary

-- Add processes that are sensitive to the state that calculate certain things based on data
-- retrieved from the different registers etc.. 
-- might want to create separate components to do the memory polling and packet parsing?

	comb: process(CurrentState)
	begin
		case CurrentState is 
			when IDLE =>
				CentralState <= "01";
				NextState <= RD;
			when RD =>
				CentralState <= "10";
				NextState <= WR;
			when WR =>
				CentralState <= "00";
				NextState <= IDLE;
			when ST3 =>
				CentralState <= "00";
				NextState <= IDLE;
		end case;
	end process comb;
	
	-- UPDATE STATE OR RESET
	seq: process(clk, rst)
	begin
		if( rising_edge(clk) and rst = '1' ) then
			CurrentState <= IDLE;
		elsif( rising_edge(clk) ) then
			CurrentState <= NextState;
		end if;
	end process seq;

end RTL;

